Low-power digital circuit design for deep-submicron CMOS technology

Kumar, Mahesh and Nithin, V and Madhushankara, M (2010) Low-power digital circuit design for deep-submicron CMOS technology. In: NCIS-2010, Manipal.

[img] PDF
1.pdf - Published Version
Restricted to Registered users only

Download (378kB) | Request a copy


Power minimization of digital circuits, and yet preservation of other performance constraints is one of the key challenges encountered in the design of deep-submicron CMOS circuits. A review of power considerations in deep-submicron digital circuits, followed by various design techniques developed to achieve low power in these circuits are discussed in detail with their corresponding impacts on the circuit performance. Considering the trade-off between speed and power, these methods are investigated to obtain an optimal low power design technique.

Item Type: Conference or Workshop Item (Paper)
Uncontrolled Keywords: Low power, submicron, CMOS technology
Subjects: Information Sciences > MCIS Manipal
Depositing User: MIT Library
Date Deposited: 19 Aug 2014 09:57
Last Modified: 19 Aug 2014 09:57
URI: http://eprints.manipal.edu/id/eprint/140387

Actions (login required)

View Item View Item