Digital clock frequency multiplier using floating point arithmetic

Madhushankara, M and Chaitanya, C V S (2012) Digital clock frequency multiplier using floating point arithmetic. International Journal of Engineering and Research Development, 2 (10). pp. 1-4. ISSN 2278-067X

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Abstract

A digital clock frequency multiplier using floating point arithmetic, which generates the output clock with zero frequency error has been presented. The circuit has an unbounded multiplication factor range and low lock time. A low power mechanism has been incorporated to ensure that the overall power consumption of the circuit is less. The circuit has been designed in TSMC 65nm CMOS process for an input reference time of 0.01ns and has been verified with random multiplication factor values

Item Type: Article
Uncontrolled Keywords: Frequency multiplier, floating point, CMOS, PLL
Subjects: Information Sciences > MCIS Manipal
Depositing User: MIT Library
Date Deposited: 19 Aug 2014 10:17
Last Modified: 19 Aug 2014 10:17
URI: http://eprints.manipal.edu/id/eprint/140390

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