Sundaresan, C and Chaitanya, C V S and Venkateswaran, P R and Bhat, Somashekara and Kumar, Mohan J (2014) Design and Development of Vedic Mathematics based BCD Adder. International Journal of Applied Information Systems, 6 (9). pp. 20-21. ISSN 2249-0868

PDF Design and Development of Vedic Mathematics based BCD Adder.pdf - Published Version Restricted to Registered users only Download (602kB) | Request a copy

Abstract

In a conventional Binary Coded Decimal (BCD) representation is used in the scientific and computing calculation. Now they are also started to have impact in the processing unit. The only overhead in the converting the value from decimal to binary, processing and converting back to decimal. The direct reproduction of decimal value in computation produces the significant improvement in conversion and processing time. This paper is the extended version of Alp Arslan Bayracci and Ahmet Akkas et al of reduced delay Binary Coded Decimal (BCD) adder. When the design is simulated for the corner cases, the design was not responding as expected and we have proposed the modified design

Item Type:	Article
Uncontrolled Keywords:	BCD adder, decimal adder, higher valence adder, adder.
Subjects:	Information Sciences > MCIS Manipal
Depositing User:	MIT Library
Date Deposited:	16 Feb 2016 11:13
Last Modified:	16 Feb 2016 11:13
URI:	http://eprints.manipal.edu/id/eprint/145359

Actions (login required)

View Item