Design and Synthesis of Reduced Delay BCD

Sundaresan, C and Chaitanya, C V S and Venkateswaran, P R and Bhat, Somashekara and Kumar, Mohan J (2015) Design and Synthesis of Reduced Delay BCD. International Journal of Computer and Information Technology, 4 (1). pp. 139-144. ISSN 2279 – 0764

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Abstract

Arithmetic and memory address computation are performed using adder operations. Hence, design of adders form an important subset of electronic chip design functionality. Performance of BCD adders is to be considered with gate count, area, delay, power consumption. A new BCD adder design is attempted here to reduce the delay and thereby increasing the speed of response. BCD adder design is considered with respect to high speed addition requirement including multi operand addition, multiplication and division. The new architecture supports 64 bit and 128 bit operands and reduces the delay by adding parallelism.

Item Type: Article
Uncontrolled Keywords: Adder, BCD Adder, Carry Logic, Delay
Subjects: Information Sciences > MCIS Manipal
Depositing User: MIT Library
Date Deposited: 16 Feb 2016 11:12
Last Modified: 16 Feb 2016 11:12
URI: http://eprints.manipal.edu/id/eprint/145360

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