Lohani, Prem Kumar and Ranjani, K and Ravishankar, . and Sundaresan, C and Chaitanya, C V S (2014) Interfacing of Systemverilog and Systemc Using Transaction Level Modeling. international journal of computers & distributed systems, 4 (2). pp. 51-63. ISSN 2278-5183

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Abstract

SystemVerilog and SystemC are extensively used for design and Verification in VLSI industry. This paper propose a method to combine SystemVerilog and SystemC code in a single hardware/software simulation which allows design teams to leverage abstract representations of system function as it increases system simulations speed. This paper also purposes a method of developing generalized Noise Channel Model to mimic the real timing scenarios in communication protocols and provide physical medium timing information to higher layers using SystemC.

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