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Designing of negative edge triggered 14 transistor d-flipflop

Dhananiwala, Mayank and Sundaresan, C (2010) Designing of negative edge triggered 14 transistor d-flipflop. International Journal of Computer Applications in Engineering, Technology and Sciences, 2 (2). pp. 242-244. ISSN 0974-3596

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Abstract

The new implementation of efficient D-Flip-Flop (DFF) using less number of transitors is presented. This DFF design allows reducing power-delay product and area of the circuit, while maintaining low complexity of logic design. Performance comparison with other DFF design techniques is presented, with respect to number of devices, delay and power dissipation, showing advantages and drawbacks of proposed DFF, as compared to other methods. A variety of circuits have been implemented in 0.18μm technologies to compare the proposed structure with existing alternatives. Properties of implemented circuit are discussed and simulation results are reported. Use of a novel physical design method enables a high degree of concurrency among process, circuit, and layout development

Item Type: Article
Uncontrolled Keywords: Standard Cell, D Flip-Flop
Subjects: Information Sciences > MCIS Manipal
Depositing User: MIT Library
Date Deposited: 02 Apr 2016 14:05
Last Modified: 02 Apr 2016 14:05
URI: http://eprints.manipal.edu/id/eprint/145731

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