Novel 16-Bit and 32-Bit Group High Speed BCD Adders

Sundaresan, C and Chaitanya, C V S and Kumar, Mohan J and Venkateswaran, P R and Bhat, Somashekara (2014) Novel 16-Bit and 32-Bit Group High Speed BCD Adders. International Journal of Computer Applications, 107 (12). pp. 36-38. ISSN 0975 – 8887

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Abstract

The VLSI binary adder is the basic building block in any computation unit. It is widely used in the arithmetic logic unit, memory addressing computation and in many other places. In this paper the binary adder is presented with keeping in mind speed, power and finally area. In this paper the BCD adder is designed using the mixed approach such as hierarchical, muxing and variable grouping techniques. The design and result are presented in this paper

Item Type: Article
Uncontrolled Keywords: BCD Adder, Hierarchy, Variable grouping, adder.
Subjects: Information Sciences > MCIS Manipal
Depositing User: MIT Library
Date Deposited: 03 May 2016 15:00
Last Modified: 03 May 2016 15:00
URI: http://eprints.manipal.edu/id/eprint/145955

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