Error analysis for parallelism in artificial neuralNetwork based nanodevice modeling

Nayak, Dayananda and Puttamadappa, C and Sarkar, Subir Kumar (2009) Error analysis for parallelism in artificial neuralNetwork based nanodevice modeling. World Academy of Science Engineering and Technology, 60. pp. 1071-1073. ISSN 2070-3724

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Abstract

A soft computing tool ArtificialNeural Network (ANN) is used in the presentwork to get optimized system parameters ofGaAs and (In,Ga)As quantum wells for desireddevice characteristics. To extract the bestperformance from a device it is very essential tochoose the parameters intelligently as theperformance is controlled by them. Hence topredict the best parameters at a time it is better to think over some special computationalmethods. In addition we have applied here theparallelism in ANN to make the computationmuch faster and errors are analyzed in detail forestimate the performance of such devices. Numerous applications in the area ofsignal processing and communications requirean implementation of highly complex algorithms along with stringent requirements on the power dissipation. Therefore, development of power reduction techniques is currently of great interest. Multiple threshold CMOS circuit which has both high and low thresholdtransistors in a single chip, can be used to dealwith the leakage problem in low voltage lowpower(LVLP) and high performance applications. Dual threshold techniques can reduce leakage power by assigning a high threshold voltage to some transistors in non critical paths. Therefore, both low power and high performance can be achievedsimultaneously. Current progress in VLSI(VeryLarge Scale Integration) and the prospect of WSI(Wafer Scale Integration) are stimulating research into low-cost high-speed microelectronic parallel-processing computer architectures. Perfect devices for suchapplications are very essential and it is alsorequired that the performance of those devicesshould error free. For the past thirty years,electronic computers have grown more powerful as their basic subunit, the transistor has shrunk. In order to continue the miniaturization of circuit elements down to the nanometer scale, researchers are investigating severalalternatives, which operate based on themovement of masses of electrons in bulk matterand take advantage of quantum mechanicalphenomena that emerge on the nanometer scale,including the discretenessof electrons.

Item Type: Article
Uncontrolled Keywords: adaptive intelligent , parallelism,optimization, artificial neural network,soft computing tool
Subjects: Engineering > MIT Manipal > Instrumentation and Control
Depositing User: MIT Library
Date Deposited: 20 Oct 2016 09:52
Last Modified: 20 Oct 2016 09:52
URI: http://eprints.manipal.edu/id/eprint/147287

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