Area Efficient, Low quiescent current and low dropout voltage regulator using 180nm cmos technology

Guru, Prasad and Shama, Kumara (2016) Area Efficient, Low quiescent current and low dropout voltage regulator using 180nm cmos technology. ICTACTJjournal on Microelectronics, 2 (3). pp. 288-292. ISSN 2395-1680

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Abstract

This paper illustrates the design and implementation of a Low Drop out voltage regulator which consumes low power and occupies less area. The regulator uses single stage error amplifier hence area consuming compensation capacitor is avoided. It needs only 16μA quiescent current making it suitable for low power applications. The proposed regulator has been designed in 180nm CMOS technology and performance is tested using spice tool and layout is done using MAGIC VLSI tool. Simulation results show that the LDO has a line regulation of 0.001V/V and load regulation of 0.002V/mA. The LDO occupies an area of 70μm × 80μm and power dissipation is 20μW

Item Type: Article
Uncontrolled Keywords: Linear Regulator, Low Drop-Out, Low Power, Power Management
Subjects: Engineering > MIT Manipal > Electronics and Communication
Depositing User: MIT Library
Date Deposited: 19 Nov 2016 11:29
Last Modified: 04 Jan 2017 14:34
URI: http://eprints.manipal.edu/id/eprint/147545

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