Shailesh, Tanuja and Shailesh, K R
(2017)
*Computing static state of linear electrical networks using iteratively weighted least squares algorithm.*
In: International Conference on Advanced Computing and Communication Systems, 06/01/2017, Sri Eshwar College of Engineering Coimbatore.

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## Abstract

Abstract—In this paper a new approach for static state estimation of linear DC circuits using iteratively weighted least squares algorithm is discussed. Three cases of erroneous meter readings while measuring currents and voltage in a simple voltage divider circuit are considered for illustration. Large size of electrical networks limits the number measurements available for state estimation. With limited real time measurements and most of the times with pseudo-measurements usually with large error margins are often used instead. This work highlights the method of processing measurement errors in estimating the static state of a linear DC electrical network. The work also highlights the importance of having accurate physical topology modeling of the network and to have known standard reference to estimate magnitude of errors and identify faulty meters. With increase in non-technical losses in T&D systems there is ever increasing chance of technical losses, state estimation can be a very useful tool in minimizing both technical and non-technical losses in the T&D process

Item Type: | Conference or Workshop Item (Paper) |
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Uncontrolled Keywords: | Iteratively weighted least squares, DC circuit, State estimation, Static state estimation, weighted least squares, faulty meters, Bad data processing, Power system state estimation, Iteratively re-weighted least squares, voltage divider |

Subjects: | Engineering > MIT Manipal > Computer Science and Engineering Engineering > MIT Manipal > Electrical and Electronics |

Depositing User: | MIT Library |

Date Deposited: | 12 Jan 2017 09:24 |

Last Modified: | 12 Jan 2017 09:24 |

URI: | http://eprints.manipal.edu/id/eprint/148021 |

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