FPGA Implementation of viterbi decoder using area efficient butterfly and traceback architecture

Shweta, V (2016) FPGA Implementation of viterbi decoder using area efficient butterfly and traceback architecture. In: National Conference on Advances in Energy Conversion Technologies, 07/02/2013, MIT, Manipal.

[img] PDF
658.pdf - Published Version
Restricted to Registered users only

Download (488kB) | Request a copy

Abstract

Viterbi decoders are used to decode convolutional codes.Viterbi decoders employed in digital wireless communications are complex and require large area. With the proliferation of battery powered small devices such as cellular phones and laptop computers, area, along with speed and power dissipation, is a major concern in VLSI design. In this paper, we investigated an area efficient design of Viterbi decoders for wireless communications applications. We considered two methods, in place butterfly computation and selective update traceback, in our design. These design approaches requires lesser number of register sets in decoding process hence these are area efficient. We followed the FPGA design approach to implement the design.

Item Type: Conference or Workshop Item (Paper)
Uncontrolled Keywords: Convolution code, Viterbi decoder, traceback, butterfly computation
Subjects: Engineering > MIT Manipal > Electrical and Electronics
Depositing User: MIT Library
Date Deposited: 30 Jan 2017 13:27
Last Modified: 30 Jan 2017 13:27
URI: http://eprints.manipal.edu/id/eprint/148228

Actions (login required)

View Item View Item