Implementation of low power sram cell Structure at deep submicron technologies

Veeranki, Yedukondala Rao B and Paradhasaradhi, Damarla and Reddy, Madan Sankar G and Siva Kumar, Kuppa Pm (2017) Implementation of low power sram cell Structure at deep submicron technologies. Journal of Theoretical and Applied Information Technology, 95 (10). pp. 2182-2190. ISSN 1992-8645

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Abstract

SRAM (Static Random Access Memory) is an significant component in memory devices where refresh operation required. To achieve high speed, SRAM has been used in most of the SOC chips. To get high reliability and low power consumptions in various applications a low power Static RAM is needed. This paper concentrates on reducing the dissipation of power during write operation in CMOS Static RAM cell for various frequencies. Here different cell SRAM cell structures like single bit SRAM, Stable SRAM cell respectively implemented and those are compared with the proposed SRAM Cell construction. Generally, power indulgence happens through the write operation because of charging and dis-charging of the SRAM Cell bit line, it is the major problem in the Static RAM cell. In this work, the Static RAM cell proposed which operates at low power compared to existing models. The comparative analysis performed in the DSCH and Microwind tools by applying technology node as 180nm

Item Type: Article
Uncontrolled Keywords: SRAM, STABLE SRAM Cell, Single bit SRAM Cell, 180nm
Subjects: Engineering > MIT Manipal > Mechatronics
Depositing User: MIT Library
Date Deposited: 22 Jun 2017 08:43
Last Modified: 22 Jun 2017 08:43
URI: http://eprints.manipal.edu/id/eprint/149122

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