Mathematical Modeling of Binary Adders for Logic Level and Gate Count

Sundaresan, C and Bhat, Somashekara and Venkateswaran, P R (2018) Mathematical Modeling of Binary Adders for Logic Level and Gate Count. In: International Conference on Recent Trends in Electrical Sciences & Medical Engineering, 08/08/2017, MIT, Manipal.

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Abstract

Addition plays an important role in many applications. A wide range of binary adders are available in the literature, but most of them do not give a critical information gate count. In this paper, we propose generic mathematical equations in terms of logical level and gate count of binary adders around which further improvements have been attempted. These generic mathematical equations aid architect or researcher to quickly estimate the delay, and area for a given design. Using these mathematical equations, a software can be developed to choose a right design for the given constraint

Item Type: Conference or Workshop Item (Paper)
Uncontrolled Keywords: mathematical model, binary adders, logical level, gate count
Subjects: Engineering > MIT Manipal > Electronics and Communication
Information Sciences > MCIS Manipal
Depositing User: MIT Library
Date Deposited: 13 Mar 2018 05:35
Last Modified: 13 Mar 2018 05:35
URI: http://eprints.manipal.edu/id/eprint/150763

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