ASIC design of low power-delay product carry pre-computation based multiplier

Chaitanya, C V S and Sundaresan, C and Venkateswaran, P R and Prasad, Keerthana (2019) ASIC design of low power-delay product carry pre-computation based multiplier. Indonesian Journal of Electrical Engineering and Computer Science, 13 (2). pp. 845-852. ISSN 2502-4752

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Abstract

High speed and efficient multipliers are essential components in today’s computational circuits like digital signal processing, algorithms for cryptography and high performance processors. Invariably, almost all processing units will contain hardware multipliers based on some algorithm that fits the application requirement. Tremendous advances in VLSI technology over the past several years resulted in an increased need for high speed multipliers and compelled the designers to go for trade-offs among speed, power consumption and area. Amongst various methods of multiplication, Vedic multipliers are gaining ground due to their expected improvement in performance. A novel multiplier design for high speed VLSI applications using Urdhva-Tiryagbhyam sutra of Vedic Multiplication has been presented in this paper. The proposed architecture modeled using Verilog HDL, simulated using Cadence NCSIM and synthesized using Cadence RTL Compiler with 65nm TSMC library.The proposed multiplier architecture is compared with the existing multipliers and the results show significant improvement in speed and power dissipation

Item Type: Article
Uncontrolled Keywords: Binary Multiplication Carry Pre Computation Multiplier Architecture Operand Decomposition Vedic Mult
Subjects: Information Sciences > MCIS Manipal
Depositing User: MIT Library
Date Deposited: 07 Feb 2019 05:18
Last Modified: 07 Feb 2019 05:18
URI: http://eprints.manipal.edu/id/eprint/153196

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