Comparison of Low Current Mismatch CMOS Charge Pumps for Analog PLLs Using 180 nm Technology

Saldanha, Alan and Gupta, Vijil and Joshi, Vinod Kumar (2019) Comparison of Low Current Mismatch CMOS Charge Pumps for Analog PLLs Using 180 nm Technology. In: Soft Computing and Signal Processing, Advances in Intelligent Systems and Computing. Springer Singapore, pp. 683-692. ISBN 978-981-13-3600-3

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Abstract

We have reinvestigated the four different charge pumps (CPs) already reported in the literature and named them CP1, CP2, CP3 and CP4. These charge pumps are widely used in phase-locked loop (PLL) and have been compared for a number of parameters, mainly current mismatch, power consumption, voltage swing and the design complexity.We observed the current mismatch between the charging and discharging currents at control voltage of 0.9 V to be 3.88%, 2.7% and 3.55% for CP1, CP3 and CP4, respectively, while it is 6.96% for CP2 at control voltage of 1.3 V. At frequency of 50 MHz, CP4 consumes 377 μW power using 200 μA current source, CP3 consumes 1840μWusing 100μAcurrent source, CP1 consumes 704 μW using 80 μA current source, while CP2 consumes 756 μW power for bias voltage of 0.47 V. The voltage swing for CP1, CP2, CP3 and CP4 is obtained to be 0.2, 1.275, 0.9 and 0.3 V, respectively, at 50 MHz frequency.

Item Type: Book Section
Uncontrolled Keywords: CP · PLL · Power consumption · Current mismatch
Subjects: Engineering > MIT Manipal > Electronics and Communication
Depositing User: MIT Library
Date Deposited: 07 Feb 2019 05:21
Last Modified: 07 Feb 2019 05:21
URI: http://eprints.manipal.edu/id/eprint/153212

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