Design of modified booth based multiplier with carry pre-computation

Chaitanya, C V S and Sundaresan, C and Venkateswaran, P R and Keerthana, Prasad (2019) Design of modified booth based multiplier with carry pre-computation. Indonesian Journal of Electrical Engineering and Computer Science, 13 (3). pp. 1048-1055. ISSN 2502-4752

[img] PDF
6216.pdf - Published Version
Restricted to Registered users only

Download (460kB) | Request a copy


Arithmetic unit is the most important component of modern embedded computer systems. Arithmetic unit generally includes floating point and fixed-point arithmetic operations and trigonometric functions. Multipliers units are the most important hardware structures in a complex arithmetic unit. With increase in chip frequency, the designer must be able to find the best set of trade-offs. The ability for faster computation is essential to achieve high performance in many DSP and Graphic processing algorithms and is why there is at least one dedicated Multiplier unit in all of the modern commercial DSP processors. Tremendous advances in VLSI technology over the past several years resulted in an increased need for high speed multipliers and compelled the designers to go for trade-offs among speed, power consumption and area. A novel modified booth multiplier design for high speed VLSI applications using pre-computation logic has been presented in this paper. The proposed architecture modeled using Verilog HDL, simulated using Cadence NCSIM and synthesized using Cadence RTL Compiler with 65nm TSMC library.The proposed multiplier architecture is compared with the existing multipliers and the results show significant improvement in speed and power dissipation

Item Type: Article
Uncontrolled Keywords: Binary Multiplication, Carry Pre-Computation, Modified Booth Multiplier, Vedic Multiplier
Subjects: Information Sciences > MCIS Manipal
Depositing User: MIT Library
Date Deposited: 02 Mar 2019 08:38
Last Modified: 02 Mar 2019 08:38

Actions (login required)

View Item View Item