Design and SV Based Verification of AMBA AXI Protocol for SOC Integration

Samanth, Rashmi and Nayak, Subramanya G (2019) Design and SV Based Verification of AMBA AXI Protocol for SOC Integration. International Journal of Recent Technology and Engineering, 8 (2). pp. 1465-1469. ISSN 2277-3878

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Advanced Microcontroller Bus Architecture Advanced eXtensible Interface (AMBA AXI) provided by the ARM supports the high performance and high frequency system design. The System on Chip (SOC) Integration design needs to meet the low latency and high bandwidth challenges. The complex bridges are necessary when high frequency operations are carried out and there is a need for the interface which meets the requirement for the wide range of the applications, all such requirements without the complex bridges are provided by the AMBA AXI. The verification of such a bus protocol required to make the SOC integration most robust one. System Verilog based verification methodology provides the systematic way of verifying such a SOC to make it as a most reliable one. Also, SV based assertion makes the checking all the protocols specification easier at the verification stage. In the present paper, the general design and verification methodologies for the AXI-Bus and Memory interface for SOC integration is proposed. Verilog based memory and AXI design being done using Verilog HDL and design challenges are discussed. The proposed design implementation supports single and burst based data transfers. The AXI protocol provides the dedicated channels for memory read and write operations. In this work, single master and single slave communication using AXI protocol with 32-bit SARM are designed and implemented. The System Verilog based verification environment is setup and used for the verification IP development. And SV Assertion based verification is being done to thoroughly check the AXI protocol functionality

Item Type: Article
Uncontrolled Keywords: AMBA AXI, Bus Function Model (BFM), Design Under Test (DUT), Network on Chip (NOC), SOC Integration, SV Assertion, Verification IP
Subjects: Engineering > MIT Manipal > Electronics and Communication
Depositing User: MIT Library
Date Deposited: 07 Aug 2019 05:31
Last Modified: 07 Aug 2019 05:31

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