A Novel Low Power and Reduced Transistor Count Magnetic Arithmetic Logic Unit Using Hybrid STT-MTJ/CMOS Circuit

Barla, Prashanth and Joshi, Vinod Kumar and Bhat, Somashekara (2020) A Novel Low Power and Reduced Transistor Count Magnetic Arithmetic Logic Unit Using Hybrid STT-MTJ/CMOS Circuit. IEEE Access, 8. pp. 6877-6889. ISSN 2169-3536

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Abstract

One of the major concern for CMOS technology is the increase in power dissipation as the technology node lowers down to deep submicron region. Magnetic tunnel junction (MTJ) working on Spin transfer torque(STT)switching mechanism is recognized as one of the most promising spintronic device for post CMOS era due to its non-volatility, high speed, high endurance, CMOS compatibility and mainly the low power dissipation which can offer the solutions for the problems posed by existing CMOS technology. Wehaveproposedanovellogic-in-memory(LIM)architectureofmagneticarithmeticlogicunit(P-MALU) based on hybrid STT-MTJ/CMOS circuits. Simulation results reveal that there is significant reduction in the total power dissipation and transistor count of arithmetic unit by 28.44% and 29.16% compared to double pass transistor logic based clocked CMOS ALU design (DPTL-C2MOS-ALU), while 58.87% and 45.16% to modified magnetic arithmetic logic unit (M-MALU) respectively. Reduction in average power dissipation for logical unit is 37.61% and 52.55% along with 47.22% and 42.42% fewer transistors than DPTL-C2MOS-ALU and M-MALU design respectively. Monte-Carlo(MC) simulation is then performed by incorporating process and mismatch variations for CMOS and extracted parameters of MTJ, to study the behavior of DPTL-C2MOS-ALU, M-MALU and P-MALU designs in terms of power dissipation. All the simulation results reveal that the P-MALU is superior than other two ALU designs in terms of power dissipation,delayanddevicecount.Further,theP-MALUcircuitisextendedfor4-bitsarithmeticoperations. Electrical simulation sareperformedtoverifythefunctionalityofthedesignforhigherbitoperations which demonstrates the feasibility of the proposed design in VLSI circuits

Item Type: Article
Uncontrolled Keywords: Logic-in-memory, magnetic RAM, magnetic tunnel junction, non-volatile, tunnel magnetoresistance, spintronics, spin transfer torque
Subjects: Engineering > MIT Manipal > Electronics and Communication
Depositing User: MIT Library
Date Deposited: 07 May 2020 06:09
Last Modified: 07 May 2020 06:09
URI: http://eprints.manipal.edu/id/eprint/155093

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