A low dropout voltage regulator with a transient voltage spikes reducer and improved figure of merit

Guruprasad, . and Kumara, Shama (2020) A low dropout voltage regulator with a transient voltage spikes reducer and improved figure of merit. Turkish Journal of Electrical Engineering and Computer Sciences, 28. pp. 500-508. ISSN 1300-0632

[img] PDF
8216.pdf - Published Version
Restricted to Registered users only

Download (2MB) | Request a copy


An area efficient output capacitor-free low dropout [LDO] voltage regulator with an improved figure of merit is presented in this paper. The proposed LDO regulator consists of a novel, dynamically biased error amplifier that reduces overshoot and undershoot voltage spikes arising from abrupt load changes. Source bulk modulation is employed to enhance the current driving capability of the pass transistor. An adaptive biasing scheme is also used along with dynamic biasing to improve the current efficiency of the system. The on-chip capacitor required for proper working of the LDO regulator is only 35 pF. The proposed LDO regulator is designed and simulated in 180 nm standard CMOS technology. The LDO regulator exhibits a line regulation of 1.67 mV/V and a load regulation of 100 µV /mA. When load changes from 0 mA to 100 mA in 1 µs, an undershoot of 148 mV and an overshoot of 172 mV are observed. The measured power supply rejection ratio is 25 dB at 100 kHz. The working of the proposed LDO regulator has been tested under all process corners and Monte-Carlo statistical analysis reveals that it is robust against process variations and local mismatch.

Item Type: Article
Uncontrolled Keywords: Dynamic biasing, adaptive biasing, source bulk modulation, output capacitorless, figure of merit, low dropout voltage regulator
Subjects: Engineering > MIT Manipal > Electronics and Communication
Depositing User: MIT Library
Date Deposited: 05 Apr 2021 09:28
Last Modified: 05 Apr 2021 09:28
URI: http://eprints.manipal.edu/id/eprint/156612

Actions (login required)

View Item View Item