Design and Evaluation of a Self Write-Terminated Hybrid MTJ/CMOS Full Adder Based on LIM Structure¤

Barla, Prashanth and Joshi, Vinod Kumar and Bhat, Somashekara (2022) Design and Evaluation of a Self Write-Terminated Hybrid MTJ/CMOS Full Adder Based on LIM Structure¤. Journal of Circuits, Systems, and Computers, 31 (8). ISSN 0218-1266

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Abstract

In this paper, a power-e±cient self write-terminated hybrid full-adder (SWTHFA) has been developed using the self write-terminated write driver and an improved version of the sense ampli¯er already reported in the literature. The SWTHFA is designed using hybrid spin transfer torque-magnetic tunnel junction (STT-MTJ)/CMOS circuit based on logic-in-memory architecture. The use of a modi¯ed sense ampli¯er improves the power dissipation and output response on one hand, whereas, on the other hand, self-write-terminated write driver cuts o® the unnecessary °ow of write current in the driver circuit, thereby eliminates power wastage in SWTHFA. Proposed SWTHFA shows improvement in power saving, output response, read and write power delay product by 38.87%, 26.45%, 40.86% and 36.53%, respectively, compared to conventional write hybrid full-adder (CWHFA). Further, we performed Monte-Carlo simula�tions by incorporating process and mismatch variations for CMOS and extracted parameters of MTJ to demonstrate the feasibility of SWTHFA in low-power VLSI circuits

Item Type: Article
Uncontrolled Keywords: Logic-in-memory; magnetic tunnel junction; nonvolatile; spin transfer torque; self�write-termination
Subjects: Engineering > MIT Manipal > Electronics and Communication
Depositing User: MIT Library
Date Deposited: 08 Aug 2022 08:53
Last Modified: 08 Aug 2022 08:53
URI: http://eprints.manipal.edu/id/eprint/159060

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