Items where Author is "Barla, Prashanth"
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Number of items: 8.

Article

Barla, Prashanth and Joshi, Vinod Kumar and Bhat, Somashekara (2021) Design and analysis of SHE‑assisted STT MTJ/CMOS logic gates. Journal of Computational Electronics, 20. pp. 1964-1976. ISSN 1569-8025

Barla, Prashanth and Joshi, Vinod Kumar and Bhat, Somashekara (2021) Spintronic devices: A promising alternative to CMOS devices. Journal of Computational Electronics. pp. 805-837. ISSN 1569-8025

Barla, Prashanth and Joshi, Vinod Kumar and Bhat, Somashekara (2021) A novel self write-terminated driver for hybrid STT-MTJ/ CMOS LIM structure. Aim Shams Engineering Journal, 12. pp. 1839-1847. ISSN 2090-4479

Barla, Prashanth and Joshi, Vinod Kumar and Bhat, Somashekara (2021) A novel self write-terminated driver for hybrid STT-MTJ/ CMOS LIM structure. Aim Shams Engineering Journal, 12. pp. 1839-1847. ISSN 2090-4479

Joshi, Vinod Kumar and Barla, Prashanth and Bhat, Somashekara and Kaushik, Brajesh Kumar (2020) From MTJ Device to Hybrid CMOS/MTJ Circuits: A Review. IEEE Access, 8. ISSN 2169-3536

Barla, Prashanth and Joshi, Vinod Kumar and Bhat, Somashekara (2020) A Novel Low Power and Reduced Transistor Count Magnetic Arithmetic Logic Unit Using Hybrid STT-MTJ/CMOS Circuit. IEEE Access, 8. pp. 6876-6889. ISSN 2169-3536

Barla, Prashanth and Joshi, Vinod Kumar and Bhat, Somashekara (2020) A Novel Low Power and Reduced Transistor Count Magnetic Arithmetic Logic Unit Using Hybrid STT-MTJ/CMOS Circuit. IEEE Access, 8. pp. 6876-6889. ISSN 2169-3536

Barla, Prashanth and Joshi, Vinod Kumar and Bhat, Somashekara (2020) A Novel Low Power and Reduced Transistor Count Magnetic Arithmetic Logic Unit Using Hybrid STT-MTJ/CMOS Circuit. IEEE Access, 8. pp. 6877-6889. ISSN 2169-3536

This list was generated on Sat Jan 22 03:33:20 2022 UTC.